1. Field of the Invention
The present invention relates to a floating gate and a method of forming the same.
2. Description of the Related Art
A flash memory is a kind of nonvolatile memory. Applications of the flash memory have been extended, and a chip integration density of the flash memory has also been improved.
Products in which a flash memory is embedded in a general logic have been applied in various fields. Accordingly, it is a problem to reduce manufacturing costs and power consumption.
To reduce manufacturing costs, a chip size must be reduced and a process must be simplified. However, the chip size has been currently reduced down to 0.10 μm with the rapid development of a photo process in accordance with a design rule.
Further, production costs can be reduced not only by simplifying a process but also by eliminating a process in which failure may occur in view of a yield.
Meanwhile, in a design of a flash memory device, a floating gate requires high capacitance for the purpose of coupling a higher floating gate voltage from a control gate.
As a method for obtaining high capacitance as described above, there are methods of increasing an overlap between floating and control gates, utilizing a material with an interlayer dielectric constant, reducing the thickness of an interlayer dielectric layer, and the like.
The method of utilizing a material with an interlayer dielectric constant or reducing the thickness of an interlayer dielectric layer has a disadvantage in that a leakage current is large.
Therefore, the method of increasing an overlap between floating and control gates is mainly used to obtain high capacitance. However, the method of increasing an overlapping area has a disadvantage in that a cell area is increased.
As a method for solving these disadvantages, there is a method of increasing an overlapping area of a sidewall rather than that of a plan, which causes many problems in view of planarization.
One of such area increasing methods is a method of allowing the shape of a floating gate to be uneven.
That is, there is a method in which a floating gate is primarily formed, and a mask process is then performed such that the interior of the floating gate is removed by a predetermined thickness, thereby allowing the shape of the floating gate to be uneven.
In this case, the capacitance of a floating gate is increased in accordance with the increase of an area due to unevenness, and thus the coupling ratio of a flash memory is increased.
However, there is a problem in that a mask process must be performed twice in such a method, i.e., a process is complicated and manufacturing costs are increased.